I frame is the first frame of a video sequence, so generally the quality after transformation and quantization is higher than that of P frame and B frame. The quantization parameter QP used is also smaller than the QP used in P frame and B frame. However, for areas where there are few moving objects, it may be considered to use a larger QP to reduce coding, that is, different areas of an I-frame may have different QPs.
P-frames generally only have the result of transform and quantization of moving macroblocks. The quantization parameter QP used is larger than I-frame. As for how much can be determined according to the moving speed, if the speed is slow, the quantization parameter QP is larger than I-frame. 2, When the speed is faster, the quantization parameter QP is 3 to 4 larger than the I frame, because when the moving speed is fast, the people see it is a bit blurry, so the large image quality loss also does not feel obvious.
The result of the B-frame may not be used as a reference frame, so the quantization parameter QP of the B-frame is larger than the P-frame in order to obtain a smaller code stream.
From the above analysis, we can know that not only the QP size of the three kinds of frames is different, but QP also changes according to the motion conditions. This kind of QP control is very complicated, and the ASIC H.264 encoder does not necessarily have such a control function. Just such control can be achieved.
ISP-FPGA Filter and Sharpener Functions
ISP is a video image processing before encoding, in which the filtering intensity and sharpening intensity have a great influence on the code stream. There are many filtering algorithms, and the filtering algorithm that can both filter and preserve the edges is very complicated, and it can be convenient with FPGA. Realize different algorithms and different intensity filters and sharpeners.
Intelligent Analysis - The Intelligent Analysis Function of FPGA
Intelligent analysis mainly has two functions, image analysis and motion analysis. The motion analysis is to obtain the moving objects in the video, such as people and vehicles; the image analysis is to obtain the distribution of the motion area and the stationary area, and the code stream of the stationary area can be reduced. The intelligent analysis function of general ASIC only has motion analysis, and FPGA can implement these two functions at the same time.
Application of FPGA in Intelligent Self-adaptation
The factors affecting the code stream mainly include: scene content changes, video resolution, video frame rate, quantization parameter QP, video filter strength, image sharpening intensity, and image analysis sensitivity. When the scene content changes, the code stream will change accordingly. In order to achieve the goal of maintaining the stream stability, it is necessary to adjust other parameters at the same time. This is intelligent adaptation. Intelligent self-adaptation requires relatively complex control strategies to implement. The parameters involved in the adjustment are distributed in ISP, intelligent analysis, H.264 coding, and other links. The requirements for real-time performance are relatively high, and it is very suitable for implementation with FPGA.
The choice of FPGA
H.264 encoding is based on macroblocks, and inevitably involves the input, output, and buffering of macroblocks during processing. The data of one macroblock is 384 bytes (256 bytes of luminance data and 128 bytes of colorimetric data). If the input, output, and processing are considered in parallel, two copies, that is, 768 bytes, must be set, so 1 Kbyte is used. The storage block just meets the requirements. The storage of reference frames may include multiple reference frame macroblocks, requiring multiple memory blocks. ISPs often need to cache 1 line of pixels, 1080p has 1920 pixels per line, and 2K bytes of memory are needed.
From the analysis above, we can see that the requirements for the internal memory of FPGAs suitable for H.264 encoding and image processing are: the storage block capacity is small (for example, 1 to 2 KB), and the greater the number of storage blocks, the better; and for the multipliers. The requirement is that the greater the number, the better.
Conclusion
From the above discussion, it can be seen that reducing the encoding bitstream of video is a systematic project that involves many aspects, especially the H.264 encoder can do a lot of work. At present, we use the EP4CE115 of CYCLONEIV to achieve an average code stream of 1280×720×25fps of less than 512Kbps, and the H.264 encoding grade is mainprofilewithcabac. With the advancement of FPGA technology, more and more FPGA resources, prediction of motion macroblocks can be more and more accurate, encoding bitstream will be less and less, the next step we are ready to use CYCLONEV to achieve 1920×1080×25fps The average bitstream is less than 1024Kbps.
P-frames generally only have the result of transform and quantization of moving macroblocks. The quantization parameter QP used is larger than I-frame. As for how much can be determined according to the moving speed, if the speed is slow, the quantization parameter QP is larger than I-frame. 2, When the speed is faster, the quantization parameter QP is 3 to 4 larger than the I frame, because when the moving speed is fast, the people see it is a bit blurry, so the large image quality loss also does not feel obvious.
The result of the B-frame may not be used as a reference frame, so the quantization parameter QP of the B-frame is larger than the P-frame in order to obtain a smaller code stream.
From the above analysis, we can know that not only the QP size of the three kinds of frames is different, but QP also changes according to the motion conditions. This kind of QP control is very complicated, and the ASIC H.264 encoder does not necessarily have such a control function. Just such control can be achieved.
ISP-FPGA Filter and Sharpener Functions
ISP is a video image processing before encoding, in which the filtering intensity and sharpening intensity have a great influence on the code stream. There are many filtering algorithms, and the filtering algorithm that can both filter and preserve the edges is very complicated, and it can be convenient with FPGA. Realize different algorithms and different intensity filters and sharpeners.
Intelligent Analysis - The Intelligent Analysis Function of FPGA
Intelligent analysis mainly has two functions, image analysis and motion analysis. The motion analysis is to obtain the moving objects in the video, such as people and vehicles; the image analysis is to obtain the distribution of the motion area and the stationary area, and the code stream of the stationary area can be reduced. The intelligent analysis function of general ASIC only has motion analysis, and FPGA can implement these two functions at the same time.
Application of FPGA in Intelligent Self-adaptation
The factors affecting the code stream mainly include: scene content changes, video resolution, video frame rate, quantization parameter QP, video filter strength, image sharpening intensity, and image analysis sensitivity. When the scene content changes, the code stream will change accordingly. In order to achieve the goal of maintaining the stream stability, it is necessary to adjust other parameters at the same time. This is intelligent adaptation. Intelligent self-adaptation requires relatively complex control strategies to implement. The parameters involved in the adjustment are distributed in ISP, intelligent analysis, H.264 coding, and other links. The requirements for real-time performance are relatively high, and it is very suitable for implementation with FPGA.
The choice of FPGA
H.264 encoding is based on macroblocks, and inevitably involves the input, output, and buffering of macroblocks during processing. The data of one macroblock is 384 bytes (256 bytes of luminance data and 128 bytes of colorimetric data). If the input, output, and processing are considered in parallel, two copies, that is, 768 bytes, must be set, so 1 Kbyte is used. The storage block just meets the requirements. The storage of reference frames may include multiple reference frame macroblocks, requiring multiple memory blocks. ISPs often need to cache 1 line of pixels, 1080p has 1920 pixels per line, and 2K bytes of memory are needed.
From the analysis above, we can see that the requirements for the internal memory of FPGAs suitable for H.264 encoding and image processing are: the storage block capacity is small (for example, 1 to 2 KB), and the greater the number of storage blocks, the better; and for the multipliers. The requirement is that the greater the number, the better.
Conclusion
From the above discussion, it can be seen that reducing the encoding bitstream of video is a systematic project that involves many aspects, especially the H.264 encoder can do a lot of work. At present, we use the EP4CE115 of CYCLONEIV to achieve an average code stream of 1280×720×25fps of less than 512Kbps, and the H.264 encoding grade is mainprofilewithcabac. With the advancement of FPGA technology, more and more FPGA resources, prediction of motion macroblocks can be more and more accurate, encoding bitstream will be less and less, the next step we are ready to use CYCLONEV to achieve 1920×1080×25fps The average bitstream is less than 1024Kbps.
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